1. Technical Field of the Invention
The present invention generally relates to the field of integrated circuit (IC) and package design. More particularly, and not by way of any limitation, the present invention is directed to a system and method for providing compliant mapping between chip bond locations and package bond locations for a packaged integrated circuit.
2. Description of Related Art
Traditional IC product flow moved from IC design to package design to printed circuit board (PCB) design to manufactured product. Typically, each stage of the process was optimized in isolation of the other stages. The increasing functionality and performance of ICs, time-to-market pressures, and cost constraints, however, have challenged this traditional flow. To provide ICs having increased input/output densities and complex, high pin-count packages in a constrained time period, IC design, package design, and PCB design have become integrated so as to support a unified manufacturing flow, with a view to increasing performance and reliability, and decreasing the time-to-market and manufacturing costs.
In support of this paradigm, the functional requirements of the IC design, package design, and PCB design are optimized concurrently. In particular, in modern design flow, the package design specifications are developed and verified concurrently with the placement and routing of the actual IC circuitry and its physical pinout requirements. A physical design verification tool verifies that the mapping between chip bond locations of an IC chip and package bond locations of its package is compliant. For example, physical design verification tools can verify that the electrical connects between the chip bond locations and package bond locations are free from short circuits.
Typically, the physical verification tool comprises a series of custom executable external scripts that access and manipulate data from several electronic design automation (EDA) and related computer aided design (CAD) tools. For example, an external script may be developed to access and manipulate package design information to prepare the package design information for a verification script. A second external script may be developed to access and manipulate IC mask data information to prepare the IC mask data information for the verification script. Finally, a third external verification script may be developed to import data prepared by the other scripts and perform the design verification.
It has been found, however, that the existing external piecemeal script schemes are not without limitations. Each time a highly complex EDA/CAD database, e.g., a mask database of a chip is accessed and manipulated by a script, there is an inherent risk of corrupting the data, giving rise to errors that can reduce yield. Moreover, the tight tolerances of today's high density, multilayer packages and the ever-increasing geometric requirements of ICs adversely compound the cumulative probability of error. Therefore, the existing script schemes are error-prone and do not accurately verify compliant mapping on a consistent basis.